Ultra-thin materials boost energy efficiency up to 1,000×, supporting future integration of compute, memory, and power functions.
CDimension announced the commercial availability of its ultra-thin 2D semiconductor materials, marking a key milestone in bringing lab-scale innovation into practical, scalable use. These materials are now available for commercial sampling and integration, already being evaluated by early customers, and represent the first visible step toward CDimension’s long-term vision of vertically integrated chips that unify compute, memory, and power into a single, high-efficiency system.
As AI, robotics, quantum computing, and edge workloads grow in complexity, traditional silicon-based architectures are hitting physical and architectural limits. Rising energy costs, slower data transfer, and fragmented chiplet packaging are constraining progress across industries. CDimension is solving these challenges at the foundation, starting with new materials and leading toward a monolithic 3D architecture based on atomically-thin chiplets designed to deliver up to:
- 100× higher energy efficiency
- 100× improvement in integration density
- 10× higher system-level operating frequency through reduced parasitic
Founded by Jiadi Zhu, an MIT Ph.D. in electrical engineering with deep expertise in 2D materials and monolithic 3D integration, advised by MIT professor Tomás Palacios, director of the Microsystems Technology Laboratories and a global leader in electronic materials, CDimension combines deep technical innovation with a clear roadmap for real-world deployment.
At the core of the company’s commercial debut is a proprietary low-temperature process that enables the direct growth of ultra-thin 2D materials, such as molybdenum disulfide (MoS2), onto finished silicon wafers without damaging underlying circuitry. The resulting layers are atomically thin, low-leakage, and energy efficient, supporting dense vertical stacking and enabling new levels of integration. While 2D materials have long held promise for next-generation chips, adoption has been slowed by manufacturing and integration hurdles. CDimension’s process overcomes these challenges with a Si back-end-of-line (BEOL) compatible approach that supports uniform, wafer-scale monolayer film growth across full silicon wafers, a key step in moving 2D materials from lab experiments to scalable commercial use. In internal testing, CDimension’s materials have demonstrated up to a 1,000× improvement in transistor-level energy efficiency compared to silicon.
In addition to MoS2, CDimension provides a full suite of high-quality 2D materials, including n-type, p-type, metallic, and insulating films, via a wafer-scale deposition process compatible with silicon manufacture. This allows seamless integration with existing manufacturing workflows and forms the materials backbone of CDimension’s broader vision to unify compute, memory, and power in a single chip architecture.
CDimension’s 2D materials are now available for commercial sampling and integration at research-accessible cost. Early customers across industry and academia are already evaluating the technology in production-relevant settings and the company is expanding access to additional research and development teams.
To support early adopters, CDimension also offers customized services through its Premier Membership program, including monolayer deposition over 3D structures and on up to 12-inch arbitrary substrates for prototyping and fabricating 2D-material-based circuits.
While 2D materials are CDimension’s first commercial release, they are just the beginning. The company’s vertically integrated architecture is designed to deliver system-wide performance gains through monolithic 3D integration and localized power management. CDimension holds multiple patents and patent applications across its materials, integration methods, and chip architectures, giving system builders the hardware foundation they need to overcome today’s bottlenecks and scale for tomorrow’s demands.
For more information, visit cdimension.com.
